Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
Both RAM and ROM random access memory devices have memory cells that are typically arranged in an array of rows and columns. During operation, a row (page) is accessed and then memory cells can be randomly accessed on the page by providing column addresses. This access mode is referred to as page mode access. To read or write to multiple column locations on a page requires the external application of multiple column addresses. To increase access time, a burst mode access has been implemented. The burst mode uses an internal column address counter circuit to generate additional column addresses. The address counter begins at an externally provided address and advances in response to an external clock signal or a column address strobe signal.
Two common types of Flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration arranged in each. In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are coupled by rows to word select lines (word lines) and their drains are coupled to column bit lines. The source of each floating gate memory cell is typically coupled to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line coupled to their gates. The row of selected memory cells then place their stored data values on the column bit lines by flowing a differing current if in a programmed state or not programmed state from the coupled source line to the coupled column bit lines.
A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to word lines. However each memory cell is not directly coupled to a source line and a column bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8 to 16 each, where the memory cells in the string are coupled together in series, source to drain, between a common source line and a column bit line. The NAND architecture floating gate memory array is then accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. In addition, the word lines coupled to the gates of the unselected memory cells of each string are also driven. However, the unselected memory cells of each string are typically driven by a higher gate voltage so as to operate them as pass transistors and allowing them to pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each floating gate memory cell of the series coupled string, restricted only by the memory cells of each string that are selected to be read. Thereby placing the current encoded stored data values of the row of selected memory cells on the column bit lines.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ or 133 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. An extended form of SDRAM that can transfer a data value on the rising and falling edge of the clock signal is called double data rate SDRAM (DDR SDRAM, or simply, DDR). SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory. A synchronous Flash memory has been designed that allows for a non-volatile memory device with an SDRAM interface. Although knowledge of the function and internal structure of a synchronous Flash memory is not essential to understanding the present invention, a detailed discussion is included in U.S. patent application Ser. No. 09/627,682 filed Jul. 28, 2000 and titled, “Synchronous Flash Memory.”
Memory devices generally have a minimum read latency time that a requesting device must wait after sending the memory device the row and column address before the data is available to be read. This minimum latency is typically due to the time required by the sense amplifiers to read the data values from the memory array that has been selected by the row and column address decoders. Additionally, other delay components are also incorporated in the minimum read latency. These are typically due to such items as the delay of the column address decoding and coupling the sensed data to the external data lines through the data buffer. As these other delay components are typically small, it is common practice to equate the minimum read latency to the minimum sensing time of the sense amplifiers of the memory device.
To minimize read latency for burst accesses and/or subsequent read requests, which will often occur within the same selected row or column “page”, memory devices will typically sense all the data bits of a selected column page at once. This is generally accomplished by incorporating a large number of sense amplifiers into the memory device, allowing all the data bits of the selected column page to be read in parallel. Because of the large number of sense amplifiers, a large data bus is usually also incorporated to couple the sense amplifiers to the memory array and to the internal data buffer of the memory device. The large number of sense amplifiers and large internal data bus to pre-read the other data words of the column page are particularly important for the operation of memory devices capable of burst mode access, where sequentially addressed data words are read from the memory device on each following clock cycle after the initial request and the read latency delay.
The large number of sense amplifiers and their coupled internal memory bus can significantly increase the circuit space requirements of the memory device on the integrated circuit substrate that it is manufactured on. Generally, the larger the space required for an integrated circuit design the fewer the number of copies of the design can be placed on a substrate wafer as it is processed and later “diced” into individual “dies,” each die having a single circuit copy on it. This lowers the typical device yield of a substrate wafer, defined as the number of unflawed devices produced from a substrate wafer, by increasing the probability of a given device containing a flaw due to the larger die size. The reduced number of dies that are yielded from a substrate wafer and the increased odds of any single die containing a flaw have the effect of increasing the production cost of the resulting memory device.
Additionally, the increased number of simultaneously active sense amplifiers in an individual memory device also increases the amount of power consumption of the device by increasing the amount of current required while it is engaged in a read operation. The increased current consumption of the memory device increases the inherent level of electronic noise that is seen internal to the memory device and externally in the circuitry that surround it, increasing the probability of a noise induced read or logic error. The noise levels of a memory device often require the designer to utilize higher voltages to operate the circuit and mitigate the possibility of such an error, further increasing device power consumption and possible device feature sizes.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative circuits and methods of reading memory arrays that minimize the number of sense amplifiers and the size of the internal data bus.